1. Field
Exemplary embodiments of the present invention relate to an integrated circuit and a method for operating the same, and more particularly, to controlling of a control signal having information at a transition point.
2. Description of the Related Art
Various integrated chips such as CPUs, memories, or gate arrays receive numerous control signals. Some of the control signals have information for controlling the integrated chips at a transition point of the logic level of a control signal. Among the signals having the information at the transition point (that is, an edge) of the logic level, there is an on-die termination signal ODT, which will be first described.
FIG. 1 is a diagram illustrating parts related to an on-die termination signal in a conventional memory device.
Referring to FIG. 1, the memory device includes a buffer 110, a latency control circuit 120, and an impedance matching circuit 130.
The buffer 110 receives an on-die termination signal ODT input to an ODT PAD. The on-die termination signal ODT is applied from a memory controller to the memory device to control on/off of the impedance matching circuit 130.
The latency control circuit 120 turns on/off the impedance matching circuit 130 using the on-die termination signal ODT input through the buffer 110. The latency control circuit 120 operates in synchronization with a clock CLK. The latency control circuit 120 turns on the impedance matching circuit 130 after a predetermined clock (a clock corresponding to a latency setting value of a termination operation) from a time point (a rising edge) at which the on-die termination signal ODT has been changed from a ‘low’ level to a ‘high’ level, and turns off the impedance matching circuit 130 after a predetermined clock from a time point (a falling edge) at which the on-die termination signal ODT has been changed from a ‘high’ level to a ‘low’ level.
The impedance matching circuit 130 is turned on/off under the control of the latency control circuit 120. The impedance matching circuit 130 has a predetermined impedance value, and performs an operation of matching the impedance of a data pad DQ when the impedance matching circuit 130 is turned on.
FIG. 2 is a diagram illustrating a level of the on-die termination signal ODT and turn on/off time points of the impedance matching circuit 130.
Referring to FIG. 2, the impedance matching circuit 130 is turned on after predetermined latency from a time point when the level of the on-die termination signal ODT has been changed from ‘low’ to ‘high’. Then, the impedance matching circuit 130 is turned off after predetermined latency from a time point when the level of the on-die termination signal ODT has been changed from ‘high’ to ‘low’.
Turning on/off of the impedance matching circuit 130 is based on the transition of the on-die termination signal ODT. The rising edge of the on-die termination signal ODT has information indicating when the impedance matching circuit 130 should be turned on, and the falling edge of the on-die termination signal ODT has information indicating when the impedance matching circuit 130 should be turned off. For a time period when there is no transition of the on-die termination signal ODT, there is no change in the impedance matching circuit 130.